1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of Related Art
Typically, a semiconductor device includes a semiconductor substrate, and an electronic element and a wiring that are formed over the main surface of the semiconductor substrate. The semiconductor device may include an interlayer dielectric film. A silicon oxide film is widely used as the interlayer dielectric film. A variety of methods are available for forming a silicon oxide film. For example, a silicon oxide film may be formed by reacting a silicon compound such as silane or the like with hydrogen peroxide by a CVD method (hereinafter referred to as "planarizing silicon oxide film"). For example, this method is described in Japanese Laid-open Patent Application HEI 9-102492. The planarizing silicon oxide film has an excellent planarization characteristic.
An interlayer dielectric film that includes a planarizing silicon oxide film may have variations in film thickness depending on locations on the main surface of the semiconductor substrate. For example, the variations occur due to the following reasons.
First, the main surface of the semiconductor substrate includes a region where wirings are formed with a high wiring density and a region wherein wirings are formed with a low wiring density. The thickness of the planarizing silicon oxide film formed over the high wiring density region is generally greater than the thickness of the planarizing silicon oxide film formed over the low wiring density region, due to a high level of flowability of the planarizing silicon oxide film.
Secondly, as the number of wiring layers increases, the number of interlayer dielectric films typically increases. Each interlayer dielectric film has variations in thickness, Such thickness variations in a plurality of the interlayer dielectric films may add up where the interlayer dielectric films overlap one another. As a result, the added thickness variation becomes greater at an upper level than at a lower level of the interlayer dielectric films. As the thickness variation becomes greater, a step difference in an interlayer dielectric film becomes larger.
When a through hole is formed in an interlayer dielectric film, a resist is used. A focus margin in exposure with respect to the resist becomes smaller when the step difference in the interlayer dielectric film becomes larger. As a result, the resolution at the resist lowers. As a consequence, a designed shape of a through hole may not be formed, or in the worst case, a through hole may not be formed at all.